FIELD OF THE INVENTION
The present invention relates to a bipolar impedance converter circuit. Impedance converters are active quadrupoles with a voltage amplification of one, which are distinguished by input impedance and low output impedance. The basic function of an impedance converter is to copy a signal, via a high-impedance input, to an output having a lower internal resistance.
Typically, these converters are embodied by an operational amplifier with direct negative feedback. These impedance converters known from the prior art comprise a differential amplifier which has the highest possible gain. To attain this high gain even with low collector currents of the transistors that form the differential amplifier, a so-called active load is used in the negative feedback loop. This load comprises transistors. In the impedance converters known from the prior art, pnp transistors are used for this.
A disadvantage of these known circuits is that integrated pnp transistors, at low collector currents and high gain, require a relatively large surface area and thus have a large undesired (parasitic collector-to-substrate capacitance. It is important in impedance converters that the influence of changes in the supply voltage, whether these are changes in direct voltage or disturbances in alternating voltage, remain as slight as possible. This is not assured, however, by using pnp transistors in the known impedance converter circuits, because of the high parasitic capacitances of pnp transistors. In addition, pnp transistors are relatively slow, which causes a marked delay in the signal to be converted.